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The _PCI_EXPRESS_BRIDGE_AER_CAPABILITY structure (wdm.h) defines the PCI Express (PCIe) advanced error reporting capabilities for a PCIe bridge device. The _PCI_EXPRESS_AER_CAPABILITY structure (wdm.h) describes a PCI Express (PCIe) advanced error reporting capability structure. The _PCI_EXPRESS_AER_CAPABILITIES structure (wdm.h) describes a PCI Express (PCIe) advanced error capabilities and control register. The PCI_DEVICE_PRESENT_INTERFACE structure is reserved for system use. The _PCI_CAPABILITIES_HEADER structure (wdm.h) defines a header that is present in every PCI capability structure. Learn more about: NPEM_CAPABILITY_STANDARD The SetVirtualFunctionData routine writes data to the PCI Express (PCIe) configuration space of a virtual function (VF) on a device that supports the single root I/O virtualization (SR-IOV) interface. Learn more about: NPEM_CONTROL_SET_STANDARD_CONTROL Learn more about: NPEM_CONTROL_QUERY_STANDARD_CAPABILITIES

Learn more about: NPEM_CONTROL_ENABLE_DISABLE The GetVirtualFunctionProbedBars routine returns the values of the PCI Express (PCIe) Base Address Registers (BARs) of a device that supports the single root I/O virtualization (SR-IOV) interface. The GetResources routine returns the resources that the PCI Express (PCIe) physical function (PF) requires in order to enable virtualization on a device that supports the single root I/O virtualization (SR-IOV) interface. A device that supports the single root I/O virtualization (SR-IOV) interface can expose one or more VFs on the PCI bus. The GetLocation routine returns the device location of a PCI Express (PCIe) virtual function (VF) on a PCI bus. The GetVirtualFunctionData routine reads data from the PCI Express (PCIe) configuration space of a virtual function (VF) on a device that supports the single root I/O virtualization (SR-IOV) interface. The EnableVirtualization routine enables or disables virtualization for a PCI Express (PCIe) device that supports the single root I/O virtualization (SR-IOV) interface.

Learn more about: NPEM_CONTROL_STANDARD_CONTROL_BIT The Pci technology is not associated with any headers.